12 Oct
|
Talent bee
|
Bengaluru
12 Oct
Talent bee
Bengaluru
FPGA/RTL Engineer – Key Requirements
Verilog/VHDL design, development & verification
Xilinx Zynq/UltraScale+ & Intel FPGA
Simulation, synthesis & timing analysis
IP integration & PS-PL co-design
Board bring-up, system validation & debugging
Required Candidate profile
FPGA/RTL/MPSoC, Verilog/VHDL
Xilinx Vivado/Vitis or Intel Quartus
PS-PL integration, IP cores
C, PetaLinux, Bare Metal
SPI, I2C, UART, Ethernet, PCIe
DDR/Flash validation
📌 Tech Lead-Systems Design Engineer( FPGA & Firmware), 3+ years (Bengaluru)
🏢 Talent bee
📍 Bengaluru