Job Summary

We are looking for an experienced

SoC Verification Engineer with strong expertise in functional verification of complex SoCs and memory interfaces

, particularly

DDR and LPDDR protocols

. The ideal candidate will have hands-on experience in developing verification environments, creating test plans, writing SystemVerilog/UVM-based testbenches, and debugging complex RTL/design issues.

Key Responsibilities

- Develop and execute verification strategies and test plans for SoC level designs.

- Develop reusable

SystemVerilog/UVM-based verification environments

.

- Verify memory controller and memory interface functionality including:

- DDR4 / DDR5

- LPDDR4 / LPDDR4X

- LPDDR5 / LPDDR5X

- HBM / HBM2E / HBM3 / HBM3

E

- Develop and maintain

UVM agents, sequences, drivers, monitors, scoreboards and functional coverage models

.

- Perform protocol-level verification of memory controller, PHY interface and associated subsystems

.

- Develop constrained-random, directed and corner-case tests.

- Create and maintain functional and code coverage models and drive coverage closure.

- Perform debug and root-cause analysis of RTL, simulation and protocol-related failures.

- Work with

VIPs/models for DDR/LPDDR protocol verification and integrate them into the SoC verification environment.

- Develop

SystemVerilog Assertions (SVA)

and protocol checks where applicable.

- Perform regression management

,



failure analysis and verification sign-off.

- Collaborate with RTL designers and architects to identify design gaps and improve verification quality.

- Participate in

SoC bring-up, subsystem integration and pre-silicon validation activities.

- Contribute to verification methodology, automation and development of reusable verification components.

Required Skills

- Strong hands-on experience 6-9yrs in

SoC verification

- Excellent knowledge of

SystemVerilog and UVM

.

- Strong understanding of

DDR/LPDDR memory protocols and memory subsystem architecture

.

- Experience with one or more of:

- DDR4 / DDR5

- LPDDR4 / LPDDR4X

- LPDDR5 / LPDDR5X

- HBM / HBM2E / HBM3 / HBM3E

- Positive understanding of memory controller, PHY, initialization, training and timing concepts

.

- Experience in developing

UVM testbenches and verification components

.

- Strong knowledge of constrained-random verification, functional coverage and coverage closure

.

- Experience with simulation, debugging and regression environments

.

- Good understanding of

SoC architecture and RTL design concepts

.

- Proficiency in

SystemVerilog Assertions (SVA)

is preferred.

- Scripting experience in

Python, Perl or Tcl is an advantage.

- Experience with industry-standard EDA tools such as

VCS, Questa/ModelSim, Xcelium or equivalent.

📌 Senior SoC Verication Engineer (Bengaluru)
🏢 Sykatiya Technologies
📍 Bengaluru