Company Description LeadIC Design is a VLSI engineering company that accelerates semiconductor innovation through end-to-end chip design expertise. Founded in 2018, the company partners with global semiconductor leaders, supporting the full chip development lifecycle with solid technical ownership and predictable delivery.

With engineering teams across India and Canada, LeadIC provides custom, memory, analog, mixed-signal, digital, verification, and physical design services tailored to product-focused teams. LeadIC’s culture emphasizes accountability, quality-driven execution, and flexible engagement models that range from specialist support to turnkey project teams. The company builds long-term technical partnerships aimed at enabling silicon success for its clients.

Role Description The Memory Circuit Design Lead will drive the design and development of advanced memory circuits, from architecture definition through implementation, verification, and silicon validation. This full-time, hybrid role is based in India, with a combination of on-site collaboration and some work-from-home flexibility.

Day-to-day responsibilities include leading circuit design for SRAM, ROM, and other embedded memory IP, performing detailed analysis of timing, power, and reliability, and guiding layout teams to achieve optimal PPA and robust signoff. The role involves reviewing and refining design specifications, conducting simulations and corner analysis, driving design reviews, and ensuring that memory IP meets performance,



yield, and manufacturability requirements.

The Memory Circuit Design

Lead will mentor engineers, coordinate with cross-functional teams (analog, digital, PD, verification), and contribute to methodology and flow improvements for scalable memory design.

Qualifications

- Strong expertise in memory circuit design, including SRAM, ROM, and embedded memory architectures, sense amplifiers, bitcell design, and peripheral circuits.
- Proficiency in transistor-level design and simulation using industry-standard EDA tools (e.g., Cadence Virtuoso, Spectre, HSPICE, or similar), including corner, Monte Carlo, and variability analysis.
- Experience collaborating with layout teams on custom and memory layout, with solid understanding of layout-dependent effects, DRC/LVS, and design-for-manufacturability practices.
- Knowledge of timing, power, and signal integrity analysis for memory IP, including interaction with STA, power analysis, and reliability teams for signoff.
- Background in mixed-signal and digital design concepts relevant to memory interfaces, test modes, redundancy, and integration into larger SoC or IP subsystems.
- Proven ability to lead technical teams, mentor engineers, conduct design and code reviews, and drive projects to completion with strong ownership.
- Experience working with cross-functional VLSI teams (analog, digital, verification, physical design) across the full chip development lifecycle.

📌 Memory Circuit Design Lead 8 to 20 Years (Bengaluru)
🏢 leadIC Design
📍 Bengaluru