Your Role and Responsibilities:

- Collaborate with micro architect, designers to implement CPU micro architectural features to solve PPA problems on targeted workloads.
- Collaborate with Silicon Bringup team and Software team to verify and debug microarchitecture and its performance.
- Strong ability to communicate and drive to closure micro architectural proposals within Core and Cache team with technical stakeholders across Chip/System with presentation and documents.
- Strong collaborative and interpersonal skills and a proven ability to guide new design team members

Required Education:

Bachelor's Degree

Preferred Education:

Master's Degree

Required Technical and Professional Expertise:

- 5-10 years experience in high performance microprocessor architecture, micro architecture, computer architecture.
- Deep knowledge of Processor Instruction set architecture (e.g ARM, X86, Power).
- Deep understanding/experience of CPU microarchitecture and architecture with experience in: Fetch, Decode, Load-Store, L1, L2 caches, Prefetch, Coherency




- Memory Design, Memory Ordering Rules, Load- Store, Pipeline optimization, PPA optimization are additionally preferred.
- Strong RTL design expertise and hands-on experience of Processor/Asic design flow: design, verification, PD synthesis, ECO, bring up.

Preferred Technical and Skilled Experience:

- Advanced Static Timing: Deep understanding of static timing and its application in chip logic development can be advantageous in driving business results.
- Front-end Processing Expertise: Familiarity with front-end processing and its role in chip logic development can be valuable in shaping the future of cognitive systems logic design.
- Post-Si debug: Familiarity with Post-Si debugs is preferable.
- Performance & Power Analysis: Familiarity with analysing Performance & Power Tools data and coming up with features solving PPA issues.

*Years of Experience:*5 - 10

📌 Logic Design Engineer (Bengaluru)
🏢 IBM
📍 Bengaluru