Jb details

Engineering / Physical Design

India

Full time

Hybrid

We are seeking an experienced SC Physical Verificatin Engineer t drive physical verificatin signff fr next-generatin lgic, memry-centric SCs, and advanced-nde designs. The candidate will be respnsible fr ensuring tapeut-ready silicn thrugh cmprehensive DRC, LVS, ERC, PERC, DFM, reliability verificatin, and manufacturability signff, while cllabrating clsely with Physical Design, CAD, RTL, Prduct Engineering, EDA vendrs, and fundry teams.

This rle requires a strng hands-n technical leader wh can drive methdlgy, executin, and signff while cllabrating clsely with Architecture, BUMP, RDL ruting and PD team cllabratin.

Key Respnsibilities

- Own and drive full-chip and hierarchical / blck physical verificatin signff, including DRC, LVS, ERC, PERC, Antenna, DFM, Density, Metal Fill, CMP, and Reliability Checks.

- Debug, custmize, and deply fundry-qualified rule decks, manage waivers, and ensure clean signff clsure fr advanced-nde designs.

- Perfrm reliability verificatin including ESD, Latch-up, Electrmigratin (EM), Flating Nets, Multi-Pwer Dmain, and Cnnectivity Checks.

- Supprt parasitic RC extractin and crrelatin f verificatin results with implementatin and silicn measurements.

- Develp and maintain physical verificatin autmatin, regressin infrastructure, scripting framewrks, and AI-assisted wrkflws.

- Wrk clsely with PD, CAD, RTL, Prduct Engineering, EDA vendrs, and fundries (including direct TSMC interactin) frm prject kick-ff thrugh tapeut.





Required / Preferred Qualificatins

- Experience in full-chip r blck-level physical verificatin fr advanced-nde SCs, memry, r hetergeneus integratin designs.

- Strng expertise in DRC, LVS, ERC, PERC, DFM, Antenna, Reliability Verificatin, and Physical Verificatin Signff Methdlgies.

- Experience in advanced technlgy ndes including 22nm, 16nm, 7nm, 5nm, and belw.

- Gd understanding f RTL-t-GDSII implementatin flws, extractin methdlgies, and physical design impacts n verificatin clsure.

- Strng debugging, analysis, and crss-functinal cllabratin skills.

- Familiarity with AI-assisted develpment and verificatin wrkflws.

- Experience with DRAM, Memry-Centric SCs, Chiplets, 2.5D/3D IC Integratin.

- Backgrund in CPU, GPU, High-Perfrmance Cmputing Designs.

- Knwledge f advanced-nde FEOL/BEOL rules, fundry design manuals, and DFM methdlgies.

- Expsure t pst-silicn debug, yield analysis, and silicn crrelatin activities.

- MS/PhD in Electrical Engineering, Cmputer Engineering, r related field.

- Experience develping autmatin using Pythn, Tcl, Perl, r similar scripting languages

Tls Required

- Physical Verificatin: Mentr Calibre (DRC, LVS, ERC, PERC, DFM), Synpsys IC Validatr (ICV), Cadence Pegasus.

- Implementatin & Extractin: Synpsys ICC2/Fusin Cmpiler, Cadence Innvus, Synpsys StarRC, Cadence Quantus.

- Autmatin & Analysis: Pythn, Tcl, Perl, AI/ML-enabled verificatin framewrks, and regressin infrastructure develpment tls.

📌 Principal Engineer – SoC Physical Verification Engineer (India)
🏢 Aion Silicon
📍 India