Analog Layout Engineer | 4+ Years (Bengaluru)

Analog Layout Engineer | 4+ Years (Bengaluru)

12 Oct
|
leadIC Design
|
Bengaluru

12 Oct

leadIC Design

Bengaluru

Analog Layout Engineer | 4–10 YearsCompany: LeadIC Design Pvt Ltd
Employment Type: Full time
Workplace Type: Hybrid
Location: Bengaluru,Pune, Hyderabad
Experience: 4–8 years
Notice Period: Immediate to 30 days only
About the RoleLeadIC Design is looking for experienced Analog Layout Engineers with strong expertise in full-custom analog and mixed-signal IC layout, particularly at advanced technology nodes.
The ideal candidate will have hands-on experience with TSMC 2nm, 3nm, 5nm, or 7nm technologies and a solid understanding of device matching, parasitic optimization, physical verification, and tape-out requirements.
Key Responsibilities• Design and implement full-custom analog and mixed-signal IC layouts using Cadence Virtuoso.
• Develop precision layouts for analog circuits, ensuring device matching, symmetry, and optimal floorplanning.
• Apply common-centroid, interdigitation, shielding, and other layout techniques to minimize mismatch and parasitic effects.
• Perform and debug DRC, LVS, ERC, and PEX checks to achieve layout sign-off readiness.




• Optimize parasitic resistance and capacitance while meeting performance, area, and reliability requirements.
• Collaborate with circuit designers and verification teams to resolve layout-related issues.
• Support physical verification, design iterations, and tape-out activities.
• Follow process design rules and technology-specific layout guidelines for advanced semiconductor nodes.

Required Qualifications• Experience: 4–10 years of relevant Analog Layout Engineering experience.
• Technology: Hands-on experience with TSMC 2nm / 3nm / 5nm / 7nm process nodes.
• EDA Tool: Strong proficiency in Cadence Virtuoso.
• Layout Expertise: Full-custom analog and mixed-signal IC layout.
• Physical Verification: Practical experience with DRC, LVS, ERC, and PEX.
• Core Skills: Device matching, common-centroid layout, shielding, parasitic optimization, and layout debugging.
• Tape-out: Experience supporting layout sign-off and tape-out

📌 Analog Layout Engineer | 4+ Years (Bengaluru)
🏢 leadIC Design
📍 Bengaluru

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