Design Verification Engineers
Location: Hyderabad
Hiring: SystemVerilog / UVM Verification Engineer (3+ Years)
ACL Digital is looking for a proactive Verification Engineer with 3+ years of experience to join our team in Hyderabad. You will be responsible for developing block/IP level testbenches, handling Vplan execution, regression management, real number modeling, and Gate Level Simulations (GLS). Experience with subsystem/SoC verification is a plus, and candidates must have a notice period of 0–30 days.
To apply, send your updated resume directly to
[email protected].
📌 Design Verification Engineer (Hyderabad)
🏢 ACL Digital
📍 Hyderabad