Skills

- Knowledge & Posting Location
- Physical Design
- EM
- IR

Minimum Qualification

- Bachelor of Technology (BTech)

- Relevant Experience: 10-18 Years

- Role: Sr Lead Physical Design

This position is for a senior level engineer in Full chip level Power Distribution Network Design. He shall be leading instrumental in power grid planning on SoC level for peak current requirements & to have Dynamic & Static IR drop assessment & closure.

Key Responsibilities

- Ability to Develop & run EMIR Signoff flow at SOC
- Ability to Close EMIR based on Dynamic (vectored and vectorless) & Static IR
- Can provide Feedback on Grid Robustness to SOC floorplan team
- Working with the system, PMIC and silicon package team to model the voltage response of the power delivery network.
- Model of the power delivery networks,



including on-die power gating and in-rush current profiles.
- Model of the current profiles and peak current demands of various IPs.
- Strong Skills in problem solving, scripting, data analysis and experience with EDA tools.
- Teamwork / flexibility / ability to thrive in a energetic environment are very important

Academic Credentials

- Bachelors or Master's degree in Computer/Electronics/Electrical Engineering

Locations

- Position: Sr.

Lead Physical

Design - Power/IR/EM

- Company: L&T; Semiconductor Technologies Limited
- Location: Bengaluru
- Posted On: 09 Oct 2026
- End Date: 07 Apr 2027
- Required Experience: 12 - 18 Years

📌 Sr. Lead Physical Design - Power/IR/EM E... (India)
🏢 Larsen & Toubro Infotech
📍 India