We are seeking a highly skilled SMTS Physical Design Engineer with strong expertise in physical design sign-off and advanced-node implementation. The ideal candidate will have hands-on experience with Cadence Innovus and TSMC 3nm/2nm technologies, driving block-level implementation, optimization, and sign-off closure.
Key Responsibilities
- Execute physical design sign-off activities for complex design blocks.
- Drive block-level implementation and closure using Cadence Innovus.
- Perform timing optimization, congestion analysis, and physical design debugging.
- Resolve setup/hold violations and physical implementation issues to achieve sign-off readiness.
- Analyze and address DRC and other implementation violations in coordination with relevant teams.
- Collaborate with STA, synthesis, RTL, and physical verification teams to ensure design quality.
- Support PPA optimization and closure in advanced FinFET technology nodes.
- Ensure adherence to sign-off requirements, design constraints, and project schedules.
Required Skills
- 5–10 years of hands-on experience in Physical Design.
- Strong expertise in physical design sign-off and block-level implementation.
- Proven experience with Cadence Innovus.
- Hands-on exposure to TSMC 3nm and/or 2nm process technologies.
- Strong understanding of timing closure, setup/hold analysis, and physical optimization.
- Experience with congestion management, design-rule debugging, and sign-off readiness.
- Solid understanding of advanced-node physical design methodologies and PPA trade-offs.
Preferred Qualifications
- Experience with advanced FinFET implementation challenges at 3nm/2nm.
- Exposure to sign-off STA and physical verification flows.
- Robust problem-solving skills and cross-functional collaboration experience.
Education B.E./B.Tech/M.E./M.Tech in Electronics, Electrical Engineering, VLSI, or a related discipline.
Ideal Candidate: A hands-on Physical Design Engineer with strong Innovus proficiency, proven sign-off execution experience, and practical exposure to TSMC 3nm/2nm technologies.