Company: LeadSoc Technologies

Job Title: Physical Design Engineer

Location: Bangalore, Karnataka

Experience: 4+ Years

Employment Type: Full-Time

Role Overview

LeadSoc Technologies is looking for an experienced Physical Design Engineer with 4+ years of hands-on experience in VLSI Physical Design. The ideal candidate should have strong expertise in physical implementation, timing optimization, and design closure, with experience working on advanced semiconductor design projects.

Key Responsibilities

- Perform end-to-end physical design activities, including floorplanning, power planning, placement, clock tree synthesis (CTS), routing, and physical design closure.
- Analyze and optimize timing, area, and power (PPA) to meet design specifications.
- Perform static timing analysis (STA) and resolve setup and hold timing violations.
- Work on signal integrity, congestion analysis, and optimization.
- Resolve physical design issues related to DRC, LVS, and routing.
- Perform timing and design optimization across pre-route and post-route stages.
- Collaborate with RTL, synthesis, STA, DFT, and Physical Verification teams to ensure successful design implementation.
- Support sign-off activities, including timing, power, and physical verification checks.




- Debug design issues and ensure quality deliverables within project timelines.

Required Skills
- 4+ years of hands-on experience in VLSI Physical Design.
- Strong understanding of the complete Physical Design flow.
- Experience with floorplanning, placement, CTS, routing, and timing closure.
- Positive knowledge of Static Timing Analysis (STA), setup and hold analysis, and timing optimization.
- Experience with EDA tools such as Cadence Innovus and/or Synopsys IC Compiler II.
- Familiarity with scripting languages such as Tcl and basic Unix/Linux commands.
- Understanding of CMOS fundamentals, semiconductor design flows, and physical design constraints.
- Good debugging, analytical, and problem-solving skills.

Preferred Skills
- Experience with advanced technology nodes.
- Knowledge of low-power design techniques and signal integrity analysis.
- Exposure to physical verification and sign-off methodologies.
- Experience in resolving congestion, DRC, and timing-related issues.

What We’re Looking For
- Strong technical and analytical skills.
- Ability to work collaboratively with cross-functional teams.
- Good communication and problem-solving abilities.
- A proactive approach to debugging and design optimization.

📌 Senior Physical Design Engineer (Bengaluru)
🏢 Leadsoc Technologies
📍 Bengaluru