Design Verification Engineer DDR / PCIe / UCIe / USB / GLS

Experience: 3+ Years

Location: Bangalore / Hyderabad / Noida/Chennai

Notice Period: Immediate to 30 Days preferred

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3+ years of experience in Design Verification (DV) for IP, subsystem, or SoC-level verification.
Solid experience in verification of high-speed protocols such as DDR, PCIe, UCIe, and USB.
Hands-on experience with SystemVerilog and UVM methodology.
Strong understanding of functional verification, testbench development, test-case creation, assertions, and coverage closure.
Experience in protocol-level verification, debugging, regression analysis, and issue tracking.
Valuable knowledge of Functional Coverage and Code Coverage with experience in coverage closure.




Experience with SVA (SystemVerilog Assertions) and constrained-random verification.
Exposure to GLS (Gate-Level Simulation), including SDF simulation, timing checks, X-propagation, and post-layout verification.
Good understanding of RTL design concepts, digital logic, and SoC/IP integration.
Hands-on experience with simulation and debug tools such as VCS, Xcelium, Questa/ModelSim, Verdi, or equivalent.
Robust scripting/programming skills in Python, Perl, Shell, or Tcl.
Ability to analyze failures, debug complex issues, and work closely with RTL, design, and architecture teams.

📌 Design And Verification Engineer Bengaluru
🏢 LanceSoft
📍 Bengaluru