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6 to 8 years of hands-on experience in PCB layout design.
Solid experience in high-speed, multilayer PCB layout design using Cadence Allegro.
Hands-on experience in DDR4 routing and constraint-driven PCB design.
Expertise in stack-up definition, differential pair routing, impedance-controlled routing, and length matching/delay tuning.
Experience in high-speed interfaces such as DDR, PCIe, USB, NAND, NOR and Ethernet based designs.
Ability to create and validate PCB footprints and manage component libraries in accordance with IPC standards.
Good understanding of IPC standards (IPC-2221, IPC-7351, etc.).
Robust knowledge of SMD and through-hole components, package technologies, and manufacturing constraints.
Experience in applying EMI/EMC design guidelines and PCB layout best practices.
Valuable understanding of Design for Manufacturability (DFM) and Design for Testability (DFT) requirements.
Ability to work closely with hardware design, SI/PI, mechanical, and manufacturing teams during board development.