Job Openings:
Lead Physical Design Engineer 7+ Years
Manager Physical Design 12+ Years
SignOff Semiconductors is looking for experienced Physical Design professionals to lead and manage SOC Physical Design teams working on next-generation, high-performance graphics designs.
Key Responsibilities
Lead and manage teams responsible for Synthesis, Physical Design, Timing and Physical Closure.
Lead Physical Design Engineer: Lead a team of 3–4 engineers and drive technical execution.
Manager – Physical Design: Manage a team of 10+ engineers, including internal and external resources.
Responsible for ensuring the completion of the SOC chip on schedule with high QoR.
Drive physical implementation of block-level and subsystem-level designs.
Contribute to Synthesis, Power Reduction, Timing Convergence and Floorplanning activities for blocks and subsystems.
Requirements / Preferred Experience
Proven experience in Physical Design for complex SOC/ASIC projects.
Robust understanding of end-to-end Physical Design methodologies and flows.
Experience with P&R; and signoff tools such as Synopsys ICC2/ICC,
Design Compiler, PrimeTime, StarRC, Calibre and Apache RedHawk.
Experience working on 7nm and below technology nodes.
Experience in Full-Chip Floorplanning, PNR Partitioning and Bump Placement is preferred.
Experience in low-power and high-performance designs.
Exposure to Front-End design, DFX and Physical Design flows.
Solid technical problem-solving, communication and presentation skills.
Ability to work effectively with cross-functional and partner teams.
Robust ownership, self-driven approach and ability to drive improvements.
Academic Credentials
BE/B.Tech/ME/M.Tech or equivalent qualification in ECE/EEE.
Experience
Lead Physical Design Engineer
7+ years of experience in Physical Design.
Prior team-handling experience with a team of 3–4 members
Manager – Physical Design
12+ years of experience in Physical Design.
At least 3+ years of experience in people management.
Experience managing 10+ member teams.