Company Description Pronesis Technologies is a global engineering services company founded by industry veterans with a focus on doing the right thing at the right time for the right reason. The company partners with leading technology organizations worldwide to deliver high-quality, reliable solutions. Pronesis specializes in ASIC/VLSI design, SoC verification, physical design, and verification IP development.

It also provides embedded product development services, including hardware design, firmware and embedded software development. Team members join a collaborative environment that values technical excellence and long-term client partnerships.

Role Description The Physical Design Engineer will perform block-level and full-chip implementation tasks, including floorplanning, placement, clock tree synthesis, routing, and timing closure for ASIC/SoC designs.

Responsibilities include power, performance, and area optimization, working on constraint development, and resolving physical verification issues such as DRC, LVS, and antenna violations. The role involves close collaboration with front-end design, verification, and test teams to ensure design integrity, sign-off readiness, and successful tape-out. The engineer will also support documentation, participate in design reviews, and contribute to continuous improvement of physical design flows and methodologies.

Qualifications

- Robust foundation in ASIC/VLSI concepts, digital design, and SoC implementation methodologies.




- Hands-on experience with physical design flows, including floorplanning, placement, CTS, routing, and timing closure using industry-standard EDA tools.
- Knowledge of static timing analysis, signal integrity, power integrity, and low-power design techniques.
- Experience with physical verification (DRC, LVS, ERC) and familiarity with foundry design rules and technology files.
- Lead end-to-end physical design implementation from Netlist to GDSII.
- Own timing closure, Static Timing Analysis (STA), and optimization of setup and hold violations.
- Optimize Power, Performance, and Area (PPA) to meet design targets and project milestones.
- Analyze and resolve signal integrity, crosstalk, congestion, IR drop, and electromigration (EM) issues.
- Perform physical verification, including Design Rule Checking (DRC) and Layout Versus Schematic (LVS) coordination.
- Debug complex physical design challenges and implement effective optimization strategies.
- Collaborate with RTL, synthesis, DFT, STA, and sign-off teams to ensure smooth design integration.
- Drive design quality, methodology improvements, and execution within project timelines.
- Provide technical guidance and mentorship to junior engineers.

Be part of a team that's pushing the boundaries of semiconductor innovation!

- Bachelor’s or Master’s degree in Electrical Engineering, Electronics, VLSI, or a related field.

📌 Physical Design Engineer (Ahmedabad)
🏢 Pronesis Technologies
📍 Ahmedabad