We are seeking a highly motivated DFT Engineer to join our ASIC/SOC Design team. The candidate will be responsible for implementing and verifying DFT features to improve testability and manufacturing quality of complex SOC/ASIC designs.
Key Responsibilities
- Develop and implement DFT architecture for ASIC/SOC designs.
- Insert and verify Scan, MBIST, LBIST, Boundary Scan (JTAG), and Compression logic.
- Work on ATPG pattern generation and fault coverage analysis.
- Perform DFT verification, simulation, and debugging.
- Collaborate with Design, Verification, Physical Design, and Test teams.
- Analyze test coverage and optimize DFT methodologies.
- Support silicon bring-up, failure analysis, and yield improvement activities.
Mandatory Skills
- Robust hands-on experience in:
- Scan Insertion
- ATPG
- MBIST
- JTAG / Boundary Scan
- DFT Verification
- Scan Compression
- Knowledge of ASIC/SOC design flow.
- Experience with synthesis and STA concepts.
- Good understanding of digital design fundamentals.
Desired Candidate Profile
- Bachelor's/Master's Degree in Electronics/ECE/VLSI.
- Experience in ASIC/SOC development projects.
- Good debugging and problem-solving skills.
- Excellent communication and stakeholder management skills.