Role Overview In this role, you will contribute to the verification of cutting-edge SoCs and IPs targeting AI, HPC, and Networking applications. You will work closely with experienced verification engineers and architects to develop testbenches, create test scenarios, analyze coverage, and help ensure high-quality silicon delivery.

This is an excellent opportunity for engineers who are passionate about digital design, verification methodologies, and next-generation semiconductor technologies.G7

Key Responsibilities

- Develop and execute verification test plans for IPs, subsystems, and SoC components.
- Create and maintain SystemVerilog/UVM-based verification environments.
- Write directed and constrained-random test cases to validate design functionality.
- Develop functional coverage models and assist in coverage closure activities.
- Debug simulation failures and collaborate with design engineers to resolve issues.
- Write assertions (SVA) to improve design checking and verification quality.
- Participate in regression execution, result analysis, and reporting.
- Support IP integration and subsystem-level verification activities.
- Learn and apply industry-standard verification methodologies and best practices.
- Contribute to automation scripts for regression, reporting, and verification productivity.




- Work closely with Design, Architecture, and Software teams to understand requirements and verify functionality.

Required Expertise

- Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or related field.
- 7+ years of experience in Design Verification.
- Solid understanding of digital design fundamentals and computer architecture.

Knowledge of

1. Verilog/SystemVerilog
2. UVM methodology
3. Simulation and debugging concepts
4. Functional and code coverage
5. Basic scripting (Python, Perl, Shell, or TCL)

- Familiarity with verification tools from Synopsys, Cadence, or Siemens EDA.
- Understanding of common bus protocols such as PCIe, CXL, Ethernet, UCIe, DDR protocols, is a plus.
- Good analytical and debugging skills.
- Strong communication and teamwork abilities.

Preferred Qualifications

- Internship or academic project experience in ASIC/SoC verification.
- Exposure to SystemVerilog assertions (SVA).
- Knowledge of constrained-random verification techniques.
- Experience with Python-based automation.
- Understanding of AI, HPC, or Networking architectures is a plus.
- Familiarity with Git or other version-control systems.

📌 Design Verification Engineer (Bengaluru)
🏢 TERASILICON IQ
📍 Bengaluru