Floor planning: Create a floorplan that defines the placement of different functional blocks and components on the semiconductor die to optimize power, performance, and area (PPA).
Placement: Place and optimize logic cells, memory elements, and other IP blocks on the chip according to the floorplan. Balance trade-offs between area, timing, and power consumption.
Clock Tree Synthesis (CTS): Design and implement clock distribution networks to ensure synchronized clock signals throughout the chip, minimizing clock skew and jitter.