Lead STA Engineer
Location: Bengaluru
Experience: 6–12 Years
Role Overview
We are looking for a Lead STA Engineer with solid hands-on expertise in Static Timing Analysis and timing closure for complex ASIC/SoC designs.
Key Responsibilities
• Own full-chip/block-level STA across multiple modes and corners.
• Perform setup/hold analysis, timing closure and ECO implementation.
• Develop and validate SDC constraints, clock definitions and timing exceptions.
• Analyze MMMC, OCV/AOCV/POCV, SI and clock-related timing issues.
• Drive timing correlation across Synthesis, P&R; and sign-off.
• Debug and resolve setup, hold, max transition, max capacitance and constraint violations.
• Work closely with RTL, Synthesis, Physical Design and DFT teams for timing closure.
• Drive PPA and timing optimization for high-performance SoCs.




• Develop/debug STA flows and automation using Tcl/Python/Perl.
• Support sign-off, tape-out and critical timing closure activities.

Required Skills
• 6–12 years of relevant STA experience.
• Robust hands-on expertise in Synopsys PrimeTime or equivalent STA tools.
• Solid understanding of SDC, MMMC, clocking, timing exceptions and STA fundamentals.
• Experience with OCV/AOCV/POCV, SI and advanced-node designs.
• Valuable understanding of ASIC implementation and physical design flow.
• Strong scripting skills in Tcl/Python/Perl.
• Experience in full-chip STA and timing sign-off preferred.

📌 Lead Sta Engineer Bengaluru
🏢 leadsoc technologies
📍 Bengaluru