We are looking for an experienced Lead Design Verification Engineer to join our team, This position is lead a Cluster Project team in Hyderabad.
- Familiarity with SoCs and boot flow would be helpful.
- • SV UVM based TB environment setup, usage of UVM VIPs.
- • Developing UVM sequences, tests, TB bring up and sanity regressions.
- • Familiarity with Software development flow including assembly and C is beneficial.
- • Knowledge of system-level architecture including buses like AXI/CHI/ACE5, bridges, memory controllers such as DDR5/LPDDR5/DDR4/LPDDR4
- • Knowledge of one or more protocols; PCIe, USB, Ethernet
- • Sound knowledge on UPF and power domain crossing
- • Excellent waveform debug skills using front end industry standard design tools like VCS, NCSIM, Verdi
- • Strong expertise in DFT-DV verification, like Scan clear / Mem clear / JTAG / IJTAG / Memory repair, Scan dump, ATPG etc
Experience: 9 to 25 Years Notice Period: 0 to 60 Days
Employee referrals are highly appreciated!
Please note: Mirafra does not charge any fees for job applications, interviews, or hiring, nor have we authorised anyone to collect money on our behalf.
📌 We are Hiring ODC - Lead Design Verification Engineers (Hyderabad)
🏢 Mirafra
📍 Hyderabad
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