We are hiring for one of our reputed clients for the following position. If you're interested and your experience matches the requirement, we'd love to hear from you.
Position: Synthesis Engineer
Experience: 3-6 Years
Location: Hyderabad
Contract Tenure : 12 months
We are looking for an engineer with a solid understanding of Static Timing Analysis (STA), timing constraints, and VLSI design flow. Responsibilities include developing and verifying block-level and SoC-level timing constraints, integrating IP timing constraints into SoC constraints, and debugging timing constraint issues.
Required Skills
- STA concepts and timing constraints (SDC).
- SoC and block-level constraint development and integration.
- VLSI design flow knowledge.
- Familiarity with Verilog, Liberty (.lib), LEF, and GDS.
- Basic knowledge of DRC/LVS physical verification.
- Scripting skills in Tcl, Perl, Unix Shell, or Python.