Are you a physical design expert passionate about high-frequency clocking architectures? We are seeking a Clock Tree Synthesis (CTS) Engineer with 3–5 years of hands-on experience to lead full-chip clock planning, skew/latency optimization, NDR routing, shielding, and power-aware clock tree implementation for complex SoC designs. Join our physical design team in Hyderabad and take charge of critical timing closure on cutting-edge chips!
? Interested? Send your updated resume directly to [email protected] to apply!