We’re Hiring | Physical Design Lead (PD Lead)

Location: Hyderabad

Experience: 5–15 Years

Interview Process: 2 Face-to-Face (F2F) Rounds

Job Summary :

We are looking for an experienced Physical Design Lead with strong expertise in ASIC Physical Design, Place and Route (P&R;), timing closure, and physical verification. The ideal candidate should have hands-on experience with advanced technology nodes (7nm or below), low-power design techniques, and leading physical design teams to achieve successful block-level closure.

Key Responsibilities

- Lead block-level Physical Design activities, including power grid (PG) planning, floor planning, partitioning, placement, scan chain reordering, and Clock Tree Synthesis (CTS).
- Drive timing optimization, Static Timing Analysis (STA), timing closure, and Signal Integrity (SI)-aware routing.
- Manage timing and functional Engineering Change Orders (ECOs), SI closure, and design rule closure.
- Perform and oversee physical verification activities, including Design Rule Checks (DRC), Layout Versus Schematic (LVS), and antenna checks.
- Conduct and support parasitic extraction, IR drop analysis, and signal integrity analysis.
- Implement advanced low-power design techniques, including voltage islands, power gating, and substrate-bias techniques.
- Lead and mentor a team of Physical Design Engineers, providing technical guidance and ensuring timely block-level closure.
- Collaborate with front-end ASIC design teams to resolve design, timing, and implementation issues.
- Ensure physical design quality, performance, power, and area (PPA) targets are met.




- Use scripting languages to automate workflows, improve productivity, and streamline physical design tasks.

Required Skills and Qualifications:

- 5–15 years of hands-on experience in ASIC Physical Design.
- Strong expertise in block-level Place and Route, floor planning, placement, CTS, routing, and timing closure.
- Experience working on 7nm or smaller technology nodes.
- Strong understanding of advanced low-power techniques, including voltage islands, power gating, and substrate biasing.
- Extensive experience with Cadence or Synopsys Physical Design tools.
- Proficiency in scripting languages such as TCL and Perl.
- Strong knowledge of timing analysis, signal integrity, parasitic extraction, and IR drop analysis.
- Expertise in physical verification, including DRC, LVS, and antenna checks.
- Proven ability to lead technical teams, mentor engineers, and drive block-level closure.
- Excellent communication, problem-solving, and cross-functional collaboration skills.

Preferred Qualifications

- Experience in timing closure for high-speed interfaces.
- Solid understanding of ASIC implementation flows and advanced-node design challenges.
- Experience coordinating with front-end design teams to resolve timing, functionality, and physical implementation issues.

Interview Process: Two face-to-face interview rounds in Hyderabad.

Interested candidates: Please share your updated resume highlighting your relevant Physical Design experience and advanced-node project exposure.

For further details:

Mail- [email protected]

Contact - (phone hidden)

Work Location: In person

📌 Physical design lead ( PD Lead ) (Hyderabad)
🏢 AE TalentBridge
📍 Hyderabad