ACL Digital is hiring a Physical Design Lead for block/top-level execution on 7nm / 5nm / 3nm nodes.
Mandatory Requirement:Cadence Toolchain Expertise: Solid hands-on experience in Innovus (Pamp;R) amp; Tempus (STA) is mandatory.Key Responsibilities amp; Requirements:Lead full ASIC PD flow: Floorplanning, Power Grid, CTS, Timing Closure, and Sign-off (GDSII).Drive MMMC STA, SI/crosstalk analysis, and ECO generation.Ensure zero DRC/LVS/DFM errors using Calibre / Pegasus.Strong TCL/Perl/Python scripting for flow automation.B.Tech / M.Tech in ECE, EEE, or VLSI.
📌 Physical Design Lead (8+ Years) (Bengaluru)
🏢 ACL Digital
📍 Bengaluru
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