- Write SV RTL for custom logic at the test chip top (clock, reset, FSM etc.)
- Experience in lint, cdc, rdc, UPF/LP lint checks
Positive to have skills:
- Understand requirements and create high level design document and low level micro-architecture for a test chip
- Test chip integration (hard ip, pads, custom logic, clock, reset etc.)
- Understanding of UPF
- Understanding of JTAG/IJTAG interface
- Basic understanding of DAC IP (DAC IP will be hard macro)