For a candidate with around 5 years of experience, the expectation is that they should have hands-on experience in at least 3 of the 5 areas, with ATPG and GLS being two of them.
Candidates do not necessarily need to be experts in all five areas, but their experience should clearly demonstrate core DFT work.
Prioritize candidates who have:
- Strong hands-on ATPG experience
- Hands-on Gate Level Simulation (GLS)
- Experience with Scan Insertion / Scan Architecture
- Experience with JTAG/IJTAG/Boundary Scan
- Experience with MBIST
- Good understanding of DFT implementation and test concepts
- Experience working on semiconductor/chip design projects
- Clear understanding of their individual contribution to the project