- 4-5 years of experience in building the timing constraints for IPs, blocks and Full-chip implementation in both flat/hierarchical flows.
- Experience with analyzing the timing reports and identifying both the design and constraints related issues.
- Preferred EDA tool experience: Synopsys Design Compiler/Primetime, Spyglass, Fishtail, Tweaker etc.
- Experience in timing closure of high frequency blocks & subsystems (> Ghz range )
- Valuable Understanding of DFT modes requirements for timing signoff
- Good understanding of SDC constraints, OCV, AOCV, POCV analysis.
- Strong TCL/scripting knowledge is mandatory.
📌 STA Engineer (India)
🏢 Sunrisesys
📍 India
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