Senior Design Verification Engineer

Location: Bengaluru

Experience: 5–12 Years

Role Overview

We are looking for experienced Design Verification Engineers with strong expertise in PCIe Gen5/Gen6/Gen7 verification, SystemVerilog, and UVM-based testbench development. The role involves functional verification of complex IP/SoC designs, verification planning, coverage closure, and debug of protocol-level issues.

Key Responsibilities

- Develop and maintain robust, reusable SystemVerilog/UVM-based verification environments for PCIe IP and SoC subsystems.
- Develop UVM testbenches, sequences, agents, drivers, monitors, scoreboards, and reference models.
- Verify PCIe Gen5/Gen6/Gen7 protocol functionality, transaction flows, and corner cases.
- Create verification plans, test scenarios, assertions, and functional coverage models.
- Execute simulations, debug failures, and drive functional and code coverage closure.
- Perform IP-level and SoC-level integration verification, including interface and protocol interaction testing.
- Collaborate with RTL design, architecture, and integration teams to resolve design issues and improve verification quality.





Required Technical Skills

- Experience: 5–12 years in ASIC/SoC Design Verification.
- Protocols: Robust PCIe expertise, preferably across Gen5, Gen6, and/or Gen7.
- Languages: Strong SystemVerilog and UVM.
- Verification: Testbench architecture and development, constrained-random verification, assertions, functional coverage, and coverage closure.
- Debug: Simulation debug, root-cause analysis, and waveform analysis.
- Design Scope: IP verification, SoC verification, and protocol-level verification.
- Experience with industry-standard EDA simulation and debug tools.

Preferred Qualifications

- Hands-on experience with PCIe protocol specifications and compliance-oriented verification.
- Exposure to advanced PCIe features, protocol corner cases, and high-speed interface verification.
- Strong problem-solving skills and the ability to work independently on complex verification challenges.

Education: B.E./B.Tech/M.E./M.Tech in Electronics, Electrical Engineering, or a related discipline.

📌 Senior Design Verification Engineer (Bengaluru)
🏢 Leadsoc Technologies
📍 Bengaluru