Jb details

Engineering / Physical Design

India, United Kingdm (Lndn), United Kingdm (Bristl), Mrcc, Spain

Full time

Hybrid

We are seeking a highly mtivated and experienced Principal Engineer – SC Physical Design r Chip-Level Expert t lead the implementatin f cmplex ASIC/SC designs frm architecture definitin thrugh successful tape-ut. The ideal candidate will have deep expertise in full-chip physical design, SC integratin, advanced-nde implementatin, and crss-functinal technical leadership.

This rle requires a strng hands-n technical leader wh can drive methdlgy, executin, and signff while cllabrating clsely with Architecture, RTL, Verificatin, DFT, STA, Package, and Silicn Validatin teams.

Key Respnsibilities

- Partner with Frnt-End and Architecture teams t understand chip architecture and drive physical design cnsideratins early in the develpment cycle.

- Lead full-chip physical implementatin activities including flrplanning, pwer planning, clck implementatin, place-and-rute, timing clsure, and signff.

- Drive physical design methdlgies, best-knwn methds (BKMs), checklists, and implementatin guidelines acrss prjects.

- Serve as the technical fcal pint fr physical design executin and crdinate activities acrss blck, subsystem, and tp-level implementatin teams.

- Define prject milestnes, track prgress, manage dependencies, and drive executin t meet tape-ut schedules.

- Cllabrate with STA, DFT, RTL, Verificatin, Pwer Integrity, and Packaging teams t achieve prject gals.

- Drive clsure f timing, cngestin, pwer, IR drp, EM, signal integrity, and physical verificatin requirements.

- Debug and reslve design, flw, and methdlgy issues, identifying scalable slutins and driving implementatin.

- Mentr engineers and cntribute t the cntinuus imprvement f design methdlgies and autmatin flws.





Required / Preferred Qualificatins

- B.Tech / M.Tech in Electrical Engineering, Electrnics, Cmputer Engineering, r related discipline.

- 15+ years f ASIC/SC Physical Design experience.

- Prven track recrd f multiple successful SC/ASIC tape-uts.

- Strng understanding f ASIC/SC integratin, including flrplanning, clck distributin, pwer distributin netwrks, glbal signal planning, I/O planning, and hard IP integratin.

- Experience addressing cmplex SC challenges invlving multiple vltage dmains, multiple clck dmains, ESD implementatin strategies, mixed-signal integratin, and package-aware design cnsideratins.

- Slid knwledge f hierarchical and tp-dwn design methdlgies, budgeting techniques, timing cnvergence, and physical cnvergence strategies fr large-scale SCs.

- Experience integrating IPs frm bth internal and external vendrs and driving physical implementatin requirements thrughut the design lifecycle.

- Hands-n experience with large-scale SCs exceeding >20M gates and perating at frequencies greater than 1GHz.

- Strng understanding f physical design databases, data management, and implementatin-signff cnsistency.

- Experience in advanced technlgy ndes including 22nm, 16nm, 7nm, 5nm, and belw.

- Strng leadership skills with the ability t drive executin acrss gegraphically distributed teams.

- Experience leading r cntributing t multiple successful full-chip SC tape-uts with wnership f implementatin, timing clsure, pwer integrity, physical verificatin, and signff.

Tls Required

- Synpsys: Fusin Cmpiler (FC), ICC2, PrimeTime (PT), StarRC, PrimePwer.

- Cadence: Innvus, Tempus, Vltus, Quantus.

- Physical Verificatin: Calibre, IC Validatr (ICV), Pegasus.

- Pwer Integrity & Signff: RedHawk, Vltus, PrimePwer.

- Scripting & Autmatin: TCL, Perl, Pythn, Shell scripting.

📌 Principal Engineer – SoC Physical Design or Chip-Level Expert (India)
🏢 Aion Silicon
📍 India