Role description

JD- DFT Role and Responsibilities: Person will be responsible for scan insertion, stuck_at & at-speed ATPG, scan simulations and post silicon debugging for hierarchical design. Skill Requirements: Person should have good hands-on experience in SCAN, ATPG , Scan pattern verification and also should have good understanding of scan constraints. Valuable to have: Knowledge of MBIST. Experience: 5- 10 yrs Qualifications: B.Tech/M.Tech B.Tech/B.E/M.Tech/M.E

Skills

DFT, Hierarchical Design, Post-Silicon Validation

About UST
UST is a global digital transformation solutions provider. For more than 20 years, UST has worked side by side with the world’s best companies to make a real impact through transformation. Powered by technology, inspired by people and led by purpose, UST partners with their clients from design to operation. With deep domain expertise and a future-proof philosophy, UST embeds innovation and agility into their clients’ organizations. With over 30,000 employees in 30 countries, UST builds for boundless impact—touching billions of lives in the process.

📌 Associate III - VLSI DFT SMG (Karnataka)
🏢 UST
📍 Karnataka