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Experience: 1+ yrs

Location: Hyderabad

We are looking for a detail-oriented and technically skilled Data Verification Engineer with hands-on knowledge of Verilog and Gate-Level Simulation (GLS) to support digital design verification and validation activities. The ideal candidate will have a robust foundation in digital logic, RTL design concepts, simulation methodologies, and hardware verification workflows.

This role is suited for an engineer who is passionate about semiconductor design, functional correctness, and identifying potential issues before hardware implementation. You will work with design and verification teams to validate digital circuits, analyse simulation results, investigate mismatches, and ensure design reliability throughout the development lifecycle.

Requirements

Key Responsibilities
- Develop, execute, and maintain verification test scenarios for digital hardware designs using Verilog-based environments.
- Support Gate-Level Simulation (GLS)



activities using synthesised netlists and appropriate simulation models.
- Analyse RTL and gate-level simulation results to verify design functionality and identify discrepancies.
- Review design specifications and translate functional requirements into verification scenarios.
- Debug simulation failures by analysing waveforms, signal transitions, timing behaviour, and log files.
- Investigate mismatches between RTL and gate-level simulation results and coordinate with design teams to identify root causes.
- Support simulations with timing annotation, including Standard Delay Format (SDF), where applicable.
- Identify potential timing-related issues, including setup and hold violations, glitches, and unknown signal values.
- Work with verification engineers to improve test coverage, testbench quality, and simulation reliability.
- Execute regression tests and maintain accurate records of test results,

📌 Data Verification 998 (Hyderabad)
🏢 Weekday AI
📍 Hyderabad