Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.

• 10 years of experience in memory subsystem design, integration or verification.

• Experience with DRAM protocols (HBM2e/HBM3/HBM4 or DDR/LPDDR4x/5/5X) including Joint Electron Device Engineering Council (JEDEC) timing, refresh and training sequences.

• Experience with the DFI controller-to-PHY interface, leading a feature or IP block, and mentoring engineers.

• Experience in SystemVerilog RTL, simulation and debug flows.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.

• Experience delivering configurable, reusable IP-parameterization, release packaging, integration guides and customer-facing documentation.

• Experience integrating third-party controller and PHY IP (Rambus, Cadence/Synopsys class) into production silicon.

• Experience with SECDED per pseudo-channel,



Reed–Solomon symbol correction, error queues, lane/row repair, address-folded CRC.

• Experience with UVM methodology and emulation-based pre-silicon validation, and familiarity with memory telemetry and Silicon Lifecycle Management (SLM) — per-pseudo-channel counters, link availability, continuous eye-opening monitors.

About the job:

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an prospect to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML

📌 Senior Silicon Engineer, HBM Memory Subsystem Design, Integration and Validation (Bengaluru)
🏢 Google
📍 Bengaluru