Hiring: Hardware Emulation Trainer – ASIC / SoC

We are looking for an experienced Hardware Emulation Trainer to deliver corporate technical training to embedded and semiconductor engineers.

Experience: 5+ years of relevant hands-on experience and technical training experience
Mode: VILT (Virtual Instructor-Led Training)
Duration: 120 hours
Training Material: The Table of Contents (TOC) will be provided. The trainer is expected to develop and provide the training materials, presentations, practical exercises and lab-based content aligned with the TOC.
Start Date: ASAP

Key Technical Requirements
Hands-on experience with the following commercial hardware emulation platforms:

• Cadence Palladium
• Synopsys ZeBu
• Siemens Veloce

Training Topics to Be Covered
• Hardware emulation fundamentals, architecture and workflows
• RTL readiness, Verilog/SystemVerilog and RTL debugging
• SoC validation and pre-silicon verification
• Transactors, VIP/AVIP and bus protocols such as AXI/APB
• FPGA prototyping and firmware-driven validation




• Waveform analysis, debugging and performance optimization
• ASIC design flow, synthesis and physical design fundamentals
• Hands-on lab exercises covering emulation workflows, RTL execution, debugging and SoC validation

Trainer Requirements
• Minimum 5 years of relevant hands-on experience and technical training experience.
• Ability to develop training materials and deliver interactive, practical sessions for experienced engineers.
• Experience in demonstrating technical concepts through lab-based exercises, practical demonstrations and real-world debugging scenarios.
• Robust communication skills and the ability to explain complex technical concepts effectively.

Interested candidates can share their updated CV at [email protected]

Please mention the hardware emulation platform(s) you have worked on and your relevant training experience when applying.

📌 Hardware Emulation Trainer – ASIC (India)
🏢 Theody Svadhyay Trailblazer
📍 India