Job Summary

Lead Design Engineer - Synthesis, LEC OR low-power verification flows - [ID 018]

Responsibilities

- Run and debug LEC sign off on design blocks; investigate and resolve NEQs and constraint mismatches.
- Work on Genus synthesis runs to improve QoR, debug SDC/constraint issues. Support CLP flows.
- Write and maintain ECO scripts and timing/power constraints for design blocks.
- Independently triage and document issues, escalating complex or systemic issues as needed.
- Collaborate with PD, DFT, and RTL teams to resolve cross-functional issues affecting synthesis/LEC/CLP closure.
- Prepare transparent status updates and technical summaries for internal tracking.

Requirements

- 4-7 years of hands-on experience in ASIC synthesis, LEC, and/or low-power verification flows.




- Working knowledge of Genus and Conformal (LEC and/or CLP).
- Familiarity with UPF/CPF-based power intent (IEEE 1801).
- Scripting proficiency in Tcl, Perl, or Python; comfortable in Unix/

Skills

- Synthesis, LEC OR low-power verification flows

Job Location

Pune / Bengaluru

Experience

4 - 7 Yrs

Company Name

EDA & Semiconductor R&D;

Disclaimer: This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.

📌 Lead Design Engineer - Synthesis, LEC OR low-power verification flows (Bengaluru)
🏢 Vitestork Consulting
📍 Bengaluru