- Academic Credentials: . Bachelors with 7 years of experience or Masters degree with 5 years of experience in Electrical Engineering
- Understand duration required,plan and execute as per schedule.
- Preferred Experience: .
MTS Synthesis STA silicon design Engineer
The Role:
The focus of this role is to lead by planning and executing the front end implementation of IP Subsystem and its physical partitions. This involves ownership of synthesis, LEC, CLP, prelayout STA and postlayout STA/Timing closure. Co-ordinate with design team and PNR teams. Guide team members on tenchical issues.
Key Responsibilities:
- Responsible for front end implementation of IPs which includes synthesis, LEC, CLP, prelayout STA and postlayout STA/Timing closure
- Collaborate with designer and PNR teams to achieve closure.
- Understand duration required, plan and execute as per schedule.
- Complete quality delivery for synthesis and timing closure.
- Debug and resolve technical issues
Preferred Experience:
- Highly experienced in synthesis, LEC, CLP and timing closure
- Experience in place and route (PNR) is plus.
- Prefered top level or SOC level experience
- Have handled blocks with complex designs, high frequency clocks and complex clocking
- complete understanding of timing constraints, low power aspects and concepts of DFT
- Have debug experience to solve issues.
- scripting and automation
Academic Credentials:
- Bachelors with 7 years of experience or Masters degree with 5 years of experience in Electrical Engineering
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