Job highlights

- . 4 to 10 years experience in SoC / Subsystem Design Verification . SystemVerilog and UVM . Testbench creation experience is a must . Own and drive .
- Experience of Power Aware Simulations using UPF is desirable (not a must) .
- is a must . .
- 4 to 10 years experience in SoC/Subsystem Design Verification

- SystemVerilog and UVM
- Testbench creation experience is a must

- Own and drive
- Defining/Implementation of test plans
- Debugging complex issues
- Completion of coverage including gate-level simulations

- Experience in writing SVA (SystemVerilog Assertions) is a must
- Protocol Expertise (Deep knowledge and hands-on expertise) on one or more of the following

- PCIe, UCIe, CXL, or NVMe
- AXI, ACE or CHI
- Ethernet
- DDR, LPDDR or HBM

- Should have worked on verification of at least three full-chip/subsystem DV projects
- EDA tools Synopsys VCS/ Cadence Xcelium and Verdi debugger
- Experience of Power Aware Simulations using UPF is desirable (not a must)
- Expertise with at least one scripting language (Python, Perl, Tcl, etc.) is a must Experience using one or more revision control systems like Git, Perforce, Clearcase, etc. is necessary

📌 SoC DV Engineer (Bengaluru)
🏢 Proxelera
📍 Bengaluru