- Experience level: 5+ Years.
- Work Experience in Synthesis Constraints development, LINT checks, CDC checks
- Experience in working/leading full-chip STA closure, defining mode requirements and corners for timing closure.
- Experience in Formal Verification with Synopsys Formality and / or Cadence Conformal LEC.
- Chip-level constraint development and constraint validation.
- Strong knowledge of clock tree synthesis, SI analysis.
- Robust understanding of ECO cycle .
Qualification: Bachelor/Master s Degree in Electronic/Electrical Engineering with Major in VLSI/Microelectronics