Job highlights

- Preferred Qualifications
- Required Qualifications
- Experience with advanced nodes and large SoCs.

About the Role onsemi is seeking a DFT Engineer to support the design and implementation of Design for Test (DFT) features for complex ASIC/SoC products across automotive and industrial applications. This role focuses on scan, ATPG, MBIST, and boundary scan, with close collaboration across design, PD, and test teams.

Key Responsibilities

- Develop and integrate DFT architectures including Scan, ATPG, MBIST, and JTAG
- Implement and debug DFT logic to ensure high fault coverage and test quality
- Generate and analyze ATPG patterns using industry standard tools
- Support at speed and transition fault testing
- Collaborate with RTL, Physical Design, STA, and Test Engineering teams
- Address timing, CDC, and low power DFT considerations
- Support test coverage analysis, DFT signoff, and silicon bring up

- Preferred Qualifications




- Experience with advanced nodes and large SoCs
- Exposure to physical aware DFT and test related ECOs
- Working knowledge of UPF and low power test strategies
- Required Qualifications
- 3 5 years of experience in ASIC / SoC DFT
- Robust understanding of:
- Scan, ATPG, MBIST, JTAG
- Fault models: stuck at, transition, at speed

- Hands on experience with DFT tools such as:

- Synopsys DFT Compiler / TestKompress
- Siemens Tessent or equivalent

- Familiarity with timing, CDC, and low power DFT flows
- BS/MS (B.Tech/M.Tech) in Electrical Engineering or related field

Disclaimer :This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.

📌 Senior DFT Engineer (Bengaluru)
🏢 ON Semiconductor
📍 Bengaluru