Job highlights

- Required Qualifications
- Preferred Qualifications

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PMTS Silicon Design Engineer The Role

As a PHY-V Lead , you will own physical verification sign-off, full-chip integration, and packaging interface (RDL) planning for advanced SoC programs. You will drive DRC/LVS clean tapeouts, integration quality, and sign-off predictability across complex multi-IP designs.

This role requires robust expertise in physical verification, top-level integration, and advanced packaging alignment , along with the ability to lead cross-functional execution across PD, Analog, and Packaging teams.

The Person

- Strong technical leader with deep PD + Physical Verification understanding
- Proven ownership of sign-off closure for complex SoCs
- Ability to drive execution across multiple teams and dependencies
- Detail-oriented with focus on quality, manufacturability, and schedule predictability
- Comfortable operating in high-pressure tapeout environments

Key Responsibilities

Physical Verification & Sign-off Ownership

- Drive end-to-end DRC, LVS, ERC, antenna closure at block and full-chip level
- Define and enforce sign-off methodology and quality criteria
- Own foundry rule decks, waivers, and risk assessments
- Deliver sign-off clean GDS for tapeout SoC / Full-Chip Integration

- Lead top-level integration of IPs/macros into SoC

- Own
- GDS assembly
- Hierarchical LVS reconciliation

- Resolve:

- Boundary issues
- Connectivity mismatches
- Integration conflicts





- Ensure robust integration across internal and third-party IPs RDL & Packaging Integration

- Drive RDL planning and bump mapping strategy
- Define IO escape routing and die-package interface
- Collaborate with Packaging, SI/PI, and system teams
- Enable flip-chip / 2.5D / 3D integration readiness Tapeout Execution & Tracking

- Own sign-off checklist, closure tracking, and tapeout readiness
- Lead tapeout reviews and milestone tracking
- Drive cross-team closure to meet schedule and quality targets Methodology & Flow Development

- Define and improve physical verification flows (Calibre/ICV/Pegasus)

- Drive

- Automation (TCL/Python)
- Runtime optimization
- Debug efficiency

- Establish best practices for hierarchical and incremental sign-off Debug & Issue Resolution

- Lead debug of

- Complex DRC violations
- LVS mismatches (shorts/opens/connectivity issues)

- Drive closure with PD/layout teams
- Minimize waivers and ensure risk-managed sign-off Leadership & Collaboration

- Lead and mentor PHY-V engineers
- Act as primary escalation point for sign-off issues

- Interface with

- PD / PnR teams
- Analog/layout teams

- Packaging and foundry teams

Required Qualifications
- B.Tech / M.Tech in Electronics / Electrical Engineering
- 10-15+ years in Physical Design / Physical Verification / SoC Integration

- Strong expertise in

- DRC, LVS, ERC, antenna checks
- Tools: Calibre / ICV / Pegasus

- Solid understanding of:

- Full PD flow (RTL GDS sign-off)

- Advanced process nodes (7nm and below)

Preferred Qualifications

- Experience in

- Full-chip SoC integration and GDS assembly
- RDL planning and advanced packaging flows

- Exposure to:

- IR/EM, SI/PI, PEX, reliability checks
- Chiplet / 2.5D / 3D-IC methodologies

- Strong scripting (TCL/Python) for automation

Disclaimer: This job posting has been aggregated from external source.

Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.

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