HI

We are hiring for FPGA RTL Designer / Engineer

Job Title: Engineer FPGA RTL Designer

Work Location: Hyderabad

Experience Required: 46 years

Domain: EIS / ASIC Frontend

Primary Skills: Modeling, RTL Design & Implementation

Role Overview

We are looking for an experienced FPGA RTL Designer with strong expertise in RTL design and implementation using Verilog/SystemVerilog. The ideal candidate should have a solid foundation in digital design and computer architecture, along with hands-on experience working through FPGA development flows from RTL design to bitstream generation.

The candidate will be responsible for designing, developing, implementing and supporting RTL modules for FPGA-based systems while collaborating with cross-functional hardware and engineering teams.

Essential Skills

- Solid hands-on experience in RTL design using Verilog/SystemVerilog.
- Good understanding of digital design fundamentals.
- Strong knowledge of computer architecture.




- Experience with FPGA development flows, from RTL coding through synthesis, implementation and bitstream generation.
- Experience with RTL modeling and implementation.
- Ability to analyze and troubleshoot RTL design issues.

Key Responsibilities

- Design and develop synthesizable RTL using Verilog/SystemVerilog.
- Translate functional and architectural requirements into robust RTL designs.
- Develop, integrate and maintain FPGA-based RTL modules.
- Participate in the complete FPGA development lifecycle, including:
- RTL design
- Simulation and debugging
- Synthesis
- Place and route / implementation
- Timing analysis
- Bitstream generation
- Analyze design

Thanks & Regards

Sri Lakshmi B

Senior IT Recruiter-Talent Acquisition Group

P:040-67284941 |+91 (phone hidden)| [email protected]

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