- 10+ years experience working on sub-micron (22nm and lower) nodes is required, out of which 3+ years timing closure experience is specifically needed working on advanced nodes (5nm and lower)

- In-depth knowledge of the complete Netlist-to-GDSII implementation that includes floor planning, placement, CTS, routing, pre-layout/post-layout STA, power integrity analysis, PV and sign-off

- Well versed with timing closure sign-off using DMSA (Distributed Multi-Scenario Analysis for multi-mode, multi-corner cases) that includes functional, DFT and at-speed timing constraints (SDC)

- Hands-on experience with one or more of each category of the following EDA tools

- STA Tools Synopsys Primetime (PT), PT-PX, Cadence Tempus, Ansys Path FX, Mentor Graphics SST Velocity

- PD Tools Innovus, ICC2, Fusion Compiler

- PV Tools - Calibre

- Should have worked on complete STA of at least three full-chip projects

- Should have generated ECOs for DRV cleaning and timing closure, ensuring successful tape-outs

- Skilled in custom scripting (Python, Perl, Tcl/Tk, etc.) for automation and flow development

- Collaborates and works closely with cross-functional teams, including physical design, verification, DFT, and software teams

📌 Lead STA Engineer (Bengaluru)
🏢 Proxelera
📍 Bengaluru