- Roles and Responsibilities: . 4 to 10 years hands-on experience with Zebu / Veloce/Palladium systems
- Excellent failure debug skills on emulators,experience using waveform debug tools like Verdi and interacting with designers / SW teams as needed
Roles and Responsibilities:
- 4 to 10 years hands-on experience with Zebu/Veloce/Palladium systems
- Model builds (end-to-end) synthesize RTL and compile them for the emulation system
- Test runs expertise functional and performance tests
- Excellent failure debug skills on emulators, experience using waveform debug tools like Verdi and interacting with designers/SW teams as needed
- Develop or integrate high performance transactors with the emulation test bench using SystemVerilog/UVM and C/C++
- Positive knowledge of SoC architecture (or) Graphics system architecture
- Protocol expertise in PCIe or AXI4/CHI is highly desirable (not a must)
- Proficient with at least one scripting language (Python, Perl, Shell, etc.)