Job highlights

- Required Skills & Experience

- Preferred Qualifications

- Strong understanding of DFT architecture,scan design,test compression,ATPG,and LBIST methodologies. . Hands-on experience with ATPG tools such as Siemens Tessent (Mentor TK) or equivalent.

- Experience with large-scale CPU,GPU,AI,or Server SoC products.

Senior Silicon Design Engineer - DFT ATPG

Job Summary

As a key member of the AMD Server CPU engineering team, you will play a critical role in ensuring the testability and manufacturing quality of next-generation EPYC Server SoCs. You will be responsible for Structural Design-for-Test (DFT) implementation, Automatic Test Pattern Generation (ATPG), Logic Built-In Self-Test (LBIST), and silicon bring-up support to achieve high-quality product delivery.

Key Responsibilities

- Collaborate with Architecture teams to understand and define DFT architecture requirements.

- Work closely with RTL Design teams to ensure compliance with DFT design methodologies, rules, and best practices.

- Partner with Physical Design teams to implement DFT structures and achieve timing closure for test logic.

- Develop and execute ATPG strategies for stuck-at, transition, and other fault models using advanced test compression techniques.

- Generate, simulate, and validate high-quality manufacturing test patterns.

- Analyze coverage results and drive design enhancements to maximize fault coverage and test quality.

- Perform debug and root-cause analysis of DFT, ATPG, and LBIST-related issues throughout the design cycle.

- Collaborate with Product Engineering teams to support manufacturing test program development and qualification.

- Support silicon bring-up, characterization, yield improvement, and production debug activities.

- Develop and maintain automation tools, scripts,



and flows to improve productivity and test quality.

- Drive continuous improvements in DFT methodologies, verification strategies, and automation infrastructure.

Required Skills & Experience

- Strong understanding of DFT architecture, scan design, test compression, ATPG, and LBIST methodologies.

- Hands-on experience with ATPG tools such as Siemens Tessent (Mentor TK) or equivalent.

- Experience with scan insertion, fault simulation, coverage analysis, and pattern validation.

- Good understanding of Static Timing Analysis (STA) and timing closure concepts.

- Robust debugging and problem-solving skills with the ability to identify and resolve complex design issues.

- Proficiency in scripting languages such as Perl, Python, Tcl, or Shell.

- Familiarity with ASIC/SoC development flows and semiconductor manufacturing processes.

- Excellent communication and collaboration skills with the ability to work effectively in a global cross-functional environment.

Preferred Qualifications

- Experience with large-scale CPU, GPU, AI, or Server SoC products.

- Knowledge of MBIST, JTAG, Boundary Scan, IEEE 1500, IJTAG, or related DFT technologies.

- Experience supporting silicon bring-up, failure analysis, and production ramp activities.

- Exposure to Emulation, Verification, or Physical Design flows is a plus.

Education

- B.E./B.Tech., M.E./M.Tech., or equivalent degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or related field.

- 5+ years of relevant DFT/ATPG experience for Senior Engineer level.

Disclaimer: This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.

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