CScale is building the interconnect for gigawatt-scale AI. As AI scale-up moves toward deployments spanning thousands of accelerators and dozens of racks, the network needs to deliver high bandwidth, predictable low latency, and continuous communication. CScale is building integrated optical interconnect designed for this new scale, enabling accelerators to work together like a single, much larger computer.

But at this scale, performance is only part of the challenge. Optical failures are inevitable, and the system needs to keep running. CScale is designing the interconnect for continuity. Lasers will fail.

Compute shouldn’t. The ambition is straightforward: Build AI interconnect you can take for granted. CScale came out of stealth in September 2026 with $145 million in Series C funding, bringing total funding to $188 million.

Role And Responsibilities

- Implement scan architecture and perform scan insertion and stitching at RTL and gate level, using the Siemens Tessent flow.
- Generate ATPG patterns (stuck-at, transition) and achieve the target test coverage.




- Run pattern simulation and debug failures, including mismatches in zero-delay and timing-annotated simulations.
- Verify JTAG (TAP controller, instructions and test data registers) and scan modes at RTL and gate-level simulation (GLS).
- Run DFT rule checks (DRC) and resolve violations with the design team.
- Work with the RTL, physical design and verification teams to close DFT requirements and meet timing for scan and test modes.
- Support DFT signoff checks and release of test patterns for tape-out.
- Document the DFT architecture, test modes and verification results.

Requirements

- 2 years of experience in scan implementation, verification and debug
- Hands-on experience in scan stitching, pattern generation and simulation
- Working knowledge of the Siemens Tessent flow for RTL DFT insertion and ATPG
- Experience in JTAG and scan verification at RTL and GLS

📌 DFT Engineer (Bengaluru)
🏢 CScale
📍 Bengaluru