With a wide range of industry-leading semiconductor solutions, we are enabling innovative growth in market segments in component solutions, featuring industry-leading technologies in System LSI, Memory and Foundry. Our engineers are offered a foundation to work on cutting-edge technologies such as Foundation IP Design, Mobile SoCs, Storage Solutions, AI/ML, 5G/ 6G solutions, Neural processors, Serial Interfaces, Multimedia IPs and much more.

As one of the largest R&D; centers outside Korea for Samsung Electronics, we take pride in our ability to work on some of the cutting edge technologies. Our engineers get to work across diverse domains, projects, products, clients, people and countries, and conduct research in current and emerging technology areas. Innovation and creativity are highly valued at this innovation hub, as we strive towards providing high reliability; high performance and value added services that enable Samsung Electronics deliver world-class products.

Roles and Responsibilities

Looking for bright ASIC design engineer with excellent analytical and technical skills. This role provides opportunity to participate in the ASIC development, with emphasis in DFT, coverage, timing closure and post-silicon diagnosis,

- Experience in architecting DFT - top level test pin planning, ATPG partitioning, MBIST planning and optimization, JTAG TDR planning and integration, architecting DFT clocking schemes, EFUSE planning for memory repair
- - Defining scan compression, low coverage analysis, improve test coverage for various fault models, pattern generation, simulation with SDF
- Good Experience in Top/Block, FLAT/Hier DFT insertion flow methodologies
- Executed scan & MBIST insertion,



ATPG and verification at full chip level
- Experience in timing closure in DFT modes - understanding of shift, capture timing constraints, MBIST constraints and their impacts
- Generate, review and validate DFT constraints to achieve timing closure of high speed design
- Experience in timing closure in DFT modes, RTL analysis, logic synthesis, physical design, signoff verification (STA, Formality, Simulations)
- - Exposure to analog and mixed signal IP tests such as PLLs, MIPI etc., methods of their pattern generation and verification
- - Exposure to post-silicon bring-up. Diagnosis and debug methods to arrive at fail points for logic or memory tests
- Should be able to comprehend architecture and associated limitations with respect to DFT and be able to predict the schedule, amount of task and personnel involved
- Understanding of Power Estimation/Management for DFT modes is preferred
- Mentor juniors, support periodic training sessions, work with teams across sites and cross-functional teams and lead by examples
- Strong written and oral communication skills
- Good understanding of Deep Sub Micron topics and their associated issues

Experience – 6+ Years of Experience

Qualifications

- B.Tech/B.E/M.Tech/M.E

Disclaimer

Samsung Semiconductor India Research (SSIR), a division of Samsung R&D; India - Bangalore Pvt. Ltd is dedicated to employing a diverse workforce and providing Equal Employment Opportunity to all individuals, regardless of their religion, gender, age, marital status, gender identity, status as a protected veteran, genetic information, status as a qualified individual with a disability, or any other characteristic protected by law.

📌 DFT Design Engineers (Bengaluru)
🏢 Samsung Semiconductor
📍 Bengaluru