Design Verification Engineer - UVM/System Verilog (India)

Design Verification Engineer - UVM/System Verilog (India)

15 Oct
|
The Growth Hive
|
India

15 Oct

The Growth Hive

India

:

- M.Tech/B.Tech in Electronics and Communication Engineering or related field.
- Proficiency in Verilog, System Verilog and UVM methodology.
- Ability to develop VIPs.
- Write test plans based on the feature list.
- Strong understanding of Digital Design Concepts, SoC Architecture, Processor architecture.
- Ability to debug test failures, excellent problem solving skills.
- Scripting (Perl, Python) for test automation.
- Familiarity with Simulation workplace (Synopsys, Cadence).
- Knowledge on Assertion based Verification.
- Knowledge on SystemC modelling is a plus.
- Knowledge of AMBA protocols.
- Knowledge of the C programming language is a plus.

Key Skills:

- Verilog, System Verilog, UVM
- Digital Design, SoC Architecture, Processor Architecture
- AMBA Protocols
- Scripting (Perl, Python)
- Simulation Tools (Synopsys, Cadence)

Bonus Skills:

- SystemC, PCIe/CXL/DDR/USB, C programming

📌 Design Verification Engineer - UVM/System Verilog (India)
🏢 The Growth Hive
📍 India

Reply to this offer

Impress this employer describing Your skills and abilities, fill out the form below and leave Your personal touch in the presentation letter.

Subscribe to this job alert:

Get the latest job offers by email for: design verification engineer - uvm/system verilog (india) / india

Subscribe to this job alert:

Get the latest job offers by email for: design verification engineer - uvm/system verilog (india) / india