Design Verification Engineer

Company: HrdWyr Location: Bengaluru (5 days work from office)

About HrdWyr

HrdWyr is a fabless semiconductor product company developing AI-native System-on-Chips (AISoC) for edge computing applications. Its chips are aimed at sectors including consumer electronics, electric vehicles, industrial systems, white goods and data centres, where lower power consumption and faster response times are often prioritised over raw computing performance.

About the Role

HrdWyr is building out its Design Verification team and is looking for a hands-on Verification Engineer to own testbench and testcase development for IP and SoC-level verification of ARM/RISC-V based chips. This is a new addition to a 6-member verification team, reporting directly to the Director, in a quick-paced, start-up environment where you'll be expected to work with open-ended problems and limited hand-holding.

What You Will Do

1. Write testcases and testbenches from scratch for C&SV;/UVM-based verification
2. Drive assertion-based, code coverage, and functional coverage-driven verification
3. Perform IP-level and SoC-level verification
4. Verify ARM or RISC-V processor-based SoCs
5. Carry out RTL and Gate-Level Simulation (GLS) verification
6. Work across at least 3 of: memory/flash controllers,



serial protocols (UART/I2C), timers/clock & reset/DMA modules, and debug architecture (JTAG/SWD)

What We're Looking For

1. 7+ years of hands-on experience in C&SV;/UVM-based verification (hard cutoff - candidates below 7 years will not be considered)
2. Proven expertise writing testcases and testbenches from scratch, not just executing existing suites
3. Experience with assertions, code coverage, and functional coverage-driven verification
4. IP and SoC-level verification experience, ideally on ARM or RISC-V based chips (ARM preferred)
5. RTL and GLS verification experience
6. Hands-on experience in at least 3 of: memory controllers (e.g., Flash controller), serial protocols (UART/I2C), timers/clock & reset/DMA modules, debug architecture (JTAG/SWD)
7. Experience with Xcelium is a plus (team's primary tool); flexibility to pick up other simulators is fine
8. Product company background strongly preferred - candidates purely from IT services backgrounds will not be a fit
9. Strong analytical and problem-solving skills, self-driven, comfortable with ambiguity and a start-up pace
10. Hands-on, practical experience matters more than a specific engineering degree

📌 Design Verification (Bengaluru)
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