Job highlights

- 5-12 years of experience in ASIC Physical synthesis / STA .
- . Good Experience in synthesis timing closure and interactions with DFT and PD
- Experience in formal verification with Cadence LEC .
- Experience in Spyglass Lint / CDC checks and waiver creation .
- Experience in RTL HDL languages Verilog / VHDL
- 5-12 years of experience in ASIC Physical synthesis/STA
- Expertise in Synopsys/Cadence Synthesis tools
- Expertise with STA with prime time/Tempus.
- Valuable Experience in synthesis timing closure and interactions with DFT and PD.
- Expertise in Low power flows for CLP, UPF ( Cadence low power, Unified power format)
- Experience in formal verification with Cadence LEC
- Expertise in ECO flows using conformal/Formality ECO.
- Experience in Spyglass Lint/CDC checks and waiver creation
- Experience in RTL HDL languages Verilog/VHDL.
- Understanding of RTL to GDS flow
- Expertise in Perl, TCL language

📌 Back end STA / Synthesis Professional (Bengaluru)
🏢 Sykatiya Technologies
📍 Bengaluru