Role description

Detailed Skill Set

• Bitcell Design • Design of simpler memory blocks (decoding, rowdec, SA, IO block w/o RA, WA) • Design of complex blocks like RA, WA, Rd selftime and write selftime • SPRAM/Dual Port/ROM architecture • Sense Amp Analysis(offset, pulse width, glitch, coupling etc.)" • Read/Write Selftime Analysis • Functional/Power Marginality analysis • Latch analysis • ESPCV • Power ON and power sequencing checks • Extraction, IR/EM analysis, PERC etc. – Nice to have • Timing, power, leak etc. setups(definitions, stimuli, MCF etc.) • Timing, power, leak etc. verification (current addition) • LVF analysis and implementation • Critical Path Tight Stimuli (CPTS) • Full Cut Tight Stimuli (FCTS) • FC power, timing, power, leak and comparison with CP • Decoupling CAP Ageing (char)

Skills

Calibre, Capacitor Aging Analysis, Critical Path Tight Stimuli,



Dual-Port Memory, Functional Marginality Analysis, Leakage Analysis, Parasitic Extraction, Physical Design

About UST

UST is a global digital transformation solutions provider. For more than 20 years, UST has worked side by side with the world’s best companies to make a real impact through transformation. Powered by technology, inspired by people and led by purpose, UST partners with their clients from design to operation.

With deep domain expertise and a future-proof philosophy, UST embeds innovation and agility into their clients’ organizations. With over 30,000 employees in 30 countries, UST builds for boundless impact—touching billions of lives in the process.

📌 Associate III - VLSI MCD ST (Bengaluru)
🏢 UST
📍 Bengaluru