- 3+ years experience in IC verification,including experience with constrained-random,coverage driven verification environments .
- Experience developing and working with object oriented verification languages anyone (System Verilog,UVM)
- . A solid understanding of object-oriented concepts and experience designing class-based test benches . .
- 3+ years experience in IC verification, including experience with constrained-random, coverage driven verification environments
- Experience developing and working with object oriented verification languages anyone (System Verilog,UVM).
- A solid understanding of object-oriented concepts and experience designing class-based test benches
- Excellent written and oral communication skills.
- Strong debugging skills.
- Solid C/C++, Perl, and scripting skills.
- Experience with formal verification tools, hardware design and debug, SystemC and other programming languages are a plus.
- Experience working with OVM, or Specman e is a plus.
- Experience working with Emulators, Accelerators and FPGA based prototyping a plus.