16 Oct
|
Leadsoc Technologies
|
Bengaluru
16 Oct
Leadsoc Technologies
Bengaluru
Technical Architect – Design for Test (DFT)
Location: Bengaluru
Experience: 12–16 Years
Role Overview
We are seeking a highly experienced Technical Architect – DFT to define and drive DFT architecture, methodology, and implementation for complex ASIC/SoC designs. The role requires deep technical expertise in MBIST, ATPG, scan insertion, and end-to-end DFT sign-off, with ownership of test architecture, coverage optimization, and design-for-manufacturing requirements.
Key Responsibilities
• Define and drive DFT architecture and test strategies for complex IP and SoC designs.
• Own scan architecture, scan insertion, scan compression, and DFT RTL integration.
• Architect and implement MBIST solutions, including memory test algorithms, controller integration, and verification.
• Drive ATPG pattern generation, fault simulation, pattern validation, and test coverage closure.
• Develop DFT specifications, implementation plans, and sign-off methodologies.
• Optimize stuck-at, transition-delay, and other relevant fault coverage while managing test time and pattern volume.
• Drive DFT rule checking, testability analysis, and resolution of DFT violations.
• Collaborate with RTL, Physical Design, Verification, and Silicon Validation teams to ensure seamless DFT integration.
• Debug DFT-related issues and support silicon bring-up, manufacturing test, and yield improvement.
• Evaluate DFT flows, establish reusable methodologies, and provide technical guidance to engineering teams.
Required Technical Skills
• 12–16 years of hands-on experience in DFT architecture and implementation for ASIC/SoC designs.
• Strong expertise in DFT architecture, scan insertion, and ATPG.
• In-depth experience with MBIST architecture, integration, and verification.
• Robust understanding of scan compression, scan-chain architecture, and test-point insertion.
• Hands-on experience with ATPG pattern generation, fault modeling, fault simulation, and coverage analysis.
• Expertise in DFT rule checking, te
📌 Technical Architect – Design for Test (Bengaluru)
🏢 Leadsoc Technologies
📍 Bengaluru